The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices which are able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET). The FinFET gets its name from the fin-like structure (fin element) which extends from a substrate on which it is formed, and which is used to form the FET channel. FinFETs three-dimensional structure allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. However, conventional methods to make FinFET devices may still have certain drawbacks. For example, in the formation of FinFET devices, trenches are formed between fin elements of the FinFET devices, which are then filled with a material. As the widths of the trenches get smaller, gaps (e.g. air pockets) are formed in the material filling the trenches. Such gaps may cause various issues during subsequent processes, resulting in flaws in subsequent formed features. This affects the quality of performance of the FinFET devices. Thus, the existing techniques have not proved entirely satisfactory in all respects.